Quote:
Originally Posted by Rst7
Updated "text" diagrams:
Code:
move.l (a0),d0 ;M1
move.l (a1),d1 ;M2
68020 clock:
01234567890123456789012345678....
Color clock (chipram slots):
[00][01][02][03][04][05][06]
ARRRRRRRM1ARRRRRRRRRM2
ARRRRRRRRRRRM1ARRRRRRRRM2
ARRRRRRRRRRM1ARRRRRRRRM2
ARRRRRRRRRM1ARRRRRRRRM2
22-25-24-23 clocks
Code:
move.l (a0),d0 ;M1
move.l d2,d3 ;M2
move.l d2,d3 ;M3
move.l (a1),d1 ;M4
68020 clock:
01234567890123456789012345678901....
Color clock (chipram slots):
[00][01][02][03][04][05][06][07]
ARRRRRRRM1M2M3ARRRRRRRRRM4
ARRRRRRRRRRM1M2M3ARRRRRRRRRM4
ARRRRRRRRRM1M2M3ARRRRRRRRRM4
ARRRRRRRRM1M2M3ARRRRRRRRRM4
26-29-28-27 clocks
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Does M1/2/3/4 means instruction prefetch?