Quote:
Originally Posted by Toni Wilen
+ write buffering by Budgie
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There are no write buffers between CPU and chipram. On the waveforms from logic analyzer, you can see that the ~RAS, ~CAS, ~WE signals are removed before the ~AS signal is removed. Therefore, the ~DSACK signal is asserted after the end of writing to the memory.
More precisely, there are no such external buffers that allow CPU to finish the write cycle before the actual write to RAM is completed.
But the CPU has its own buffer inside, and while the bus is busy with a write cycle, instructions from cache can be executed. For example, look to Figure 8-6 from the datasheet.