Here's another, which I don't understand. DIVL.L expects a CHK expection? Then OK: No exception generated. I would expect an 5, as D1 is zero.
Code:
DIVL.L (default):
DIVL.L/0000.dat (default). 0...
40850000 4c7b 1fbf 7666 divs.l (lab_4085006a,pc,d7.w*8),d7:d1
40850006 4afc illegal
S 4086b782 39.49.00.00.e4.00*b3.00.86.00.00.8c.13.15.c4.59.00.00.00.65
SR: expected 801f -> 8010 but got 801a (fff2)
Trace (6 stacked) SR mismatch: 8010 != 8010
Trace (6 stacked) PC mismatch: 40850004 != 40166b4c
Exception: expected 6 but got no exception.
Registers before:
D0: 000014aa D1:*00000000 D2: 7fff777e D3: 0ffff7d0
D4: 95555080 D5: 80810100 D6: 00010101 D7:*dc6f36e3
A0: 00000000 A1: 0000008c A2: 0000801e A3: 00007fff
A4: 7fffff0a A5: c03fffff A6: 4084ff00 A7: 40800400
SR:!801f PC: 40850000 ISP: 40800800 MSP: 40800880
T1=1 T0=0 S=0 M=0 X=1 N!1 Z*1 V!1 C*1
Registers after:
D0: 000014aa D1:*763f4285 D2: 7fff777e D3: 0ffff7d0
D4: 95555080 D5: 80810100 D6: 00010101 D7:*e42e6200
SR:!801a/201a PC: 40850006 ISP: 40800800 MSP: 00000000
T1=1 T0=0 S=0 M=0 X=1 N!1 Z*0 V!1 C*0
INTREQ: c000 INTENA: c000
OK: No exception generated
3983 (1/2) S=0 E05=6 E09=6 E25=771 E26=257 E27=771 E28=1028 E29=514 E30=514
CPUlvl=2, Mask=ffffffff Code=40850000 SP=40800400 ISP=40800880
Low: 00000000-00007fff High: ffffffff-fffffffe
Test: 40800000-4089ffff Safe: ffffffff-fffffffe