[KK/Altair]

Blitter B B B x B B B B x B B B B x B B B B x

I'm pretty sure the Blitter can only ever access memory in cycles of certain parity, with remaining ones either dedicated to internal operations or idle. So, a simple AB->D blit would last for 6 bus cycles, making 3 bus accesses during that time.

So the AB->D no-display example really becomes:

         0       4       8       12      16      20     
CPU      r C - C - C - C - C - C - C - C - C -
Blitter  B - B - B - B - B - B - B - B - B - B

So, AFAIK, when there are no other devices competing for memory, CPU could skip a cycle to align perfectly with the cycles inaccessible to Blitter. Then both are running full speed and the nasty bit doesn't even matter (until scanline hits cycles reserved exclusively for FDD and audio).



Your display-on diagrams are in agreement with my knowledge so far, because 4bpp display uses only the cycles the Blitter can't use.

but it is a very small modification to the code

Well, this part is done in asm and the controlling code is split in multiple parts that get launched from IRQ, making even small modifications quite nasty.

And please excuse me for clogging your thread with lengthy posts containing untested ideas

On the contrary - keep them coming.

If you are going to target a stock A500 then maybe you should consider reducing the screen height to increase frame rate?

I'm not sure this would be a clean win. You'd probably have to cut height by 25% to start feeling the difference at all, which would be quite a lot.

I did the same kind thing to increase performance of my Quake 2 port to AGA.

Nice. Great work on that.

If you use a Doom style status bar at the bottom of the screen and a smaller one at the top then you could get away with a 320x180 or maybe 320x160 pixel 3D viewport.

Might be worth a try. I was also considering adding option to just reduce screen size, but this would also scale things and reduce already limited readability.