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Originally Posted by dissident
... Chip memory won't be cached in any case ...
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Yes, maybe my phrase in not written well, I meant to express this concept
If I don't remember wrong, some accelerators (wrongly) enable data cache for chip ram, causing various problems.
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As the vanilla A1200/020 has no data cache, there's nothing to worry about. 
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Sure, also here pieces are missing..; I had to begin the phrase with: "Fortunately for the A1200 at least the
code in chip ram can go in icache" et cetera..
Never take anything for granted and complete your thoughts
When you write in rush..
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It is enabyled by the ESS bit in the PCR register of the 68060 not in the CACR.
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Right.
In my "disable all" code I zero ESS in PCR register.
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This buffer can't be disabled separatly in any of the 68060 registers.
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I've no manual at hand,but I also do not remember this "Push Buffer" bit.
Later I'll take a look.
