Hi dissident, to be even more precise (a bit pedantic?) chipmem
data accesses are uncached.
This is fundamental in vanilla A1200 where you can interleave code in cache with any DMA access (Blitter et al.), even when BLTPRI is set, at full speed.
In A500 you need to disable BLTPRI to work the same technique (so a slower overall).
There is a good explanation of chip cacheability in WHDLoad docs:
http://www.whdload.de/docs/en/cache.html#chipmem
And yes, all accesses to the internal bus must comply with these rules (CHIP RAM, CUSTOM CHIPS, also the bogo RAM in A500).
As always a very good note of Kalms
