Quote:
Originally Posted by Toni Wilen
Bogus interrupt should be fixed now. (Confirmed not happening in real A500)
CIA IRQ line is slightly delayed, it is possible to read set interrupt bit in ICR before chip's IRQ line gets activated. UAE internally puts interrupt trigger in a timer queue but it didn't check if it was already cleared (by CPU read of ICR) when timer expired. In this case real CIA still pulses IRQ line but as a side-effect it made emulation think CIA interrupt bit was still active and kept generating interrupt until ICR was read again (instead of generating single interrupt only).
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another step towards perfection.
Thanks!