Quote:
Originally Posted by meynaf
What ? You ask risc lovers to write actual asm code ? Ahem... 
Oh, by the way. This is a little bit boring example ; with my own instruction set it would be single instruction. But who cares.
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I do.
you mentioned instruction fusing... and maybe your instruction set would be a good intermediate representation:
a sophisticated decoder/translator in FPGA would find that both code snippets do the same in the end and can be represented by a single (intermediate) instruction.
The FPGA would take every instruction and identify the group. it can do that in parallel with many instructions.(parallelism)
In the second step it compares every instruction with the one that follows - if it belongs to the right group and such a comparison makes sense. Meanwhile the next group of instructions are passing through step one. (pipelining)
in the third step matching couples of instructions are fused - there can be more than one fusing step. (meanwhile an other group of instructions enters step one und former step one instructions go to comparing in step two....)
Now we would end up with a architecture independent and very short intermediate representation of the code.
Traversing a LUT or a tree each intermediate instruction would be translated in either host-cpu code or send to some special simd-unit in FPGA.
there could be more than one of these decoders/translators allowing for some kind of "speculative translation" of branches.