Quote:
Originally Posted by meynaf
You do not necessarily need to change the fpga's configuration for that.
You could just have some sort of ultra-wide (simd) alu.
Then when a loop is identified which has all its instructions supported there (and with no bad dependencies), it can be "rewritten" to use that special hardware.
I can tell i'd find this kind of hardware autovectorization a lot more sexy than adding dumb simd extensions to the instruction set...
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you are right: SIMD in (a new) instruction set are a must.
but this was a reply to my FPGA-CPU-hybrid emulator idea. And in this case it would need to stick to the legacy 68K ISA.
This special SIMD-Unit (reconfigurable or not) would be part of the enhanced JIT.
Even Intel is playing with this ideas:
to use Intel's own SPMD compiler to create special Cl cores in FPGAs that are more efficient than e.g. generic CL-cores in your gfx-card.
Edit: ah - "lot more sexy" instead of "not more sexy" - i misread the first time ;-)
YES: it is fascinating but a lot of work....