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Originally Posted by Megol
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Very hot hotspots could than again be compiled into VHDL for live updating the FPGA - could be working for things like a ray-tracer or fractal generator.
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That isn't really a good idea - you'd have to generate specialized 68k cores in realtime! |
(I need to come back to this one more time, since my first answer was not good enough.)
To make this clear: this is an optional optimization. It would be the 3. step and is just an idea. But this idea could be useful.
Step one: interpreted execution of code. FPGA can assist in decoding and translating. Good speed-up but slower than JIT.
Step two: JIT on host cpu. Identifying hotspots and optimizing execution. Buffering translated code.
Step three: identifying persistent hotspots and generate specialized cores in the FPGA. This needs to be done
by spare cores, that are not utilizes otherwise.
We would NOT create "specialized 68k cores" or "specialized Host-CPU cores", but rather special CL-cores or special DSPs - just capable of executing one former loop of code by sending a single instruction and a range of data.