[SpeedGeek]

** 9TH NEWS UPDATE **

FastCache040+ v1.6P5 has been removed. Phase5 68060.library
can optionally use FixMapP5 if it improves the stability of their system.

FixMapP5 1.4 ©SpeedGeek 2018 (MMU Handler ©Michael Sinz 2001)

INTRODUCTION:
FixMapP5 is a tool to modify some of the default MMU mapping of
the Phase5 68040 and 68060 libraries. This can improve stability
and prevent crashing under the following condition:

- Hardware or software interrupts which occur during a Chip RAM
access by the 68060 (In particular when Store buffer is enabled).

Software bugs which allow illegal writes to the $F80000 Standard
Kickstart ROM can cause a debugging problem in Copyback mode so this patch corrects that problem as well.

FEATURES:
- Changes Chip RAM mode to Precise (68060 only)
- Changes Standard ROM cache to Writethrough (68040 or 68060)
- Uses 68040/060 library detection code
- 100% Assembler code

REQUIREMENTS:
- Amiga with 68040 or 68060 CPU and MMU
- Phase5 68040.library or 68060.library

WARNING:
This tool was developed ONLY for use with the Phase5 libraries but
it does NOT actually verify such usage. So it can and probably
will mess up the mapping of ANY other libraries!

CREDITS:
Thanks to Michael Sinz for his freely distributable MMU handler.

HISTORY:
v1.0 - First release
v1.1 - Added code to skip mapping $F00000 space (which included $F80000 space) for CyberstormPPC, CyberstormMK3 and BlizzardPPC
v1.2 - Replaced FindName() with FindResident() since v1.1 wasn't
working at all. Also, fixed a typo on module names.
v1.3 - Swapped order of 68040/060 library test. Some OS 3.1
systems use a dummy 68040.library (which does not expunge)
and prevented the chip RAM change to precise. Thanks to
Northway for reporting this bug.
v1.4 - Added code to determine the Chip RAM start address from the system memory list. Hopefully, this solves the problem with
Kickstart versions which config the Chip RAM differently.