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Dipski · 14 April 2018, 10:56

Thanks for the reply, I didn't quite follow initially.

I removed U14 (reset button control) which didn't have any effect, and I disconnected the output on U37 in the hope it was grounding the reset line, but it is remaining low on the input side.

Just to check my process, with the U37 output disconnected (pin 8) I should still see 5V on the reset line on the input side if there is no fault (pin 8)? Is the purpose of U37 to drive the expansion port reset line low when the system is in reset, and to prevent the opposite from occurring?

I guess I'm a little stuck on how to track down the problem from here - I'm not sure what to rule in or out, with little activity on the board and all clocks working it's hard to differentiate which signals (or lack thereof) are caused by the reset state, or if one of them is the cause.

Address strobe and data strobe are high (no activity)
Processor read/write is high (no activity)
Size_0 and Size_1 are high (no activity)
No activity on the address lines
D_sack_0 and D_sack 1 are high (no activity)
CPU_br is high (no activity)
CBR_bg has no activity sitting at 3.8V
Halt is high
Reset stuck low
ROM_en and ROM_ds have no activity

Incidentally the ROM has been checked and is working.

Could the CPU hold the reset down if there's a memory fault? Can the CPU hold the reset line down due to an internal fault? Can Alice, Paula, Akiko or Lisa drag the reset line down themselves (can it only be the CPU holding it down)?

14 April 2018, 10:56	#8
Dipski Registered User Join Date: Jun 2016 Location: Victoria, Australia Posts: 32	Thanks for the reply, I didn't quite follow initially. I removed U14 (reset button control) which didn't have any effect, and I disconnected the output on U37 in the hope it was grounding the reset line, but it is remaining low on the input side. Just to check my process, with the U37 output disconnected (pin 8) I should still see 5V on the reset line on the input side if there is no fault (pin 8)? Is the purpose of U37 to drive the expansion port reset line low when the system is in reset, and to prevent the opposite from occurring? I guess I'm a little stuck on how to track down the problem from here - I'm not sure what to rule in or out, with little activity on the board and all clocks working it's hard to differentiate which signals (or lack thereof) are caused by the reset state, or if one of them is the cause. Address strobe and data strobe are high (no activity) Processor read/write is high (no activity) Size_0 and Size_1 are high (no activity) No activity on the address lines D_sack_0 and D_sack 1 are high (no activity) CPU_br is high (no activity) CBR_bg has no activity sitting at 3.8V Halt is high Reset stuck low ROM_en and ROM_ds have no activity Incidentally the ROM has been checked and is working. Could the CPU hold the reset down if there's a memory fault? Can the CPU hold the reset line down due to an internal fault? Can Alice, Paula, Akiko or Lisa drag the reset line down themselves (can it only be the CPU holding it down)?