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Old 29 June 2017, 21:05   #253
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Join Date: Jun 2015
Location: Germany
Posts: 402
Well, the 080 core has normal DMA (start address, destination address, number of bytes, pull trigger, go) already in case facts about the present state are of any interest here. DMA should go through the cache for coherency such that there is again no real difference when comparing to a second CPU. Just try to see the 2nd thread as a flexibly programmable DMA controller and one that uses all resources that are currently not used by the main thread: it's completely for free! You could also use it as a software blitter doing pixel format conversion on-the-fly and much more.
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