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Old 29 June 2017, 17:48   #228
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Join Date: Jun 2015
Location: Germany
Posts: 402
Originally Posted by meynaf View Post
But i'll follow your argument and then tell you there isn't any more bandwidth available for SMP...
Playing games again badmouthing Vampire although you should know better?

The main thread could run from cache while the secondary thread could saturate the memory interface. No problem there. This plus you again fail to point out a significant difference between a secondary CPU and a DMA controller that would favour the DMA controller. Why would the DMA controller not be limited by the memory bandwidth but a second CPU would? Again no sustainable argument from you why a CPU would not be ≥ a DMA controller.
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