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Old 22 June 2017, 11:38   #161
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Originally Posted by chaos View Post
I'm not too familiar with the POWER8 arch, but your quote clearly states "GPR-to/from-VSR move operations", which would imply separate GPR & VSR regfiles. So, it looks like it does have separate 'integer-only' regular general purpose registers and separate 128x64 VSR registers. Which in my opinion, makes perfect sense, as using just a single 128x64 regfile for all ops would push power usage much higher.
Yes, of course! Addressing memory with 128 bit registers wouldn't make much sense, would it? The VSU combines the legacy FP and Altivec units into a new super-unit that also does integer stuff. In addition to this there is still the normal General Purpose Unit, otherwise the normal POWER code obviously wouldn't run. Again there is no real difference here to what Apollo does. There are still 32bit address registers in Apollo and the legacy integer unit operates on one 32bit-half of the registers.
Now, that doesn't mean that ops on VSR can't be integer, because, why wouldn't they be - even GPUs can do integer math.
This is exclusively about pointing out that Matt critisizes the Apollo ISA for something that obviously is no problem in the real world today.
The issue with separate regfiles is not (just) of frequency, but mostly power. Look at the latest Intel's AVX512 - power usage is quite a lot higher then previous versions. It just doesn't make sense to use such large regfiles for all operations.
You are talking about a 512bit unit, we are discussing how a 64bit unit supposedly is a problem for both power consumption and clock speed...

BTW, the power isn't consumed by the register file but by the super-wide and manyfold parallel ALU. We don't have anything wider than 64bits in Apollo. About what decade of processor development are we discussing here? Are we discussing about what's a good design decision today or about what seemed to be a good decision in 1995?
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