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Old 21 June 2017, 19:26   #147
Join Date: Jan 2010
Location: Kansas
Posts: 1,284
Originally Posted by grond View Post
The POWER8 has the same register design as Apollo Core, i.e. integer registers and wide SIMD registers are the same. The POWER8 runs at 5 GHz and is at the time of writing the fastest processor in the world. So you are wrong with your claim "slows down a critical path". Reality proves you wrong which is something that even non-tech savvy people should understand.
No! Wrong! The POWER8 shares the FPU and SIMD unit register files (vector scalar register file).

See Figure 1 which clearly shows the vector scalar register file which is 128x64 bits. What is the "reality" here? Was the truth relative? Will you admit you were wrong and agree with the truth?

I see nothing wrong with the unified POWER8 vector scalar register file. The argument for it is well stated in the article linked above. This arrangement could work well for a 68k FPU and SIMD unit. It is interesting that IBM did not increase the width of the SIMD unit registers which are still 128 bits (wider gives more parallelism) and they halved the number of vector registers from the gaming PPC VMX128 standard (large register files are expensive and power hungry even in the POWER8?).

There have been a few architectures which shared the integer and SIMD unit register files but they are mostly defunct including the Alpha and PA-RISC ISAs. The SIMD units would be stuck with 64 bit wide integer only registers if they were still around today (MMX/AMMX limited). The Motorola m88k RISC architecture did add floating point into the unified integer floating point register file and it was considered a huge mistake with few repeats since the 80s.
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