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Old 21 June 2017, 11:04   #97
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Join Date: Jun 2015
Location: Germany
Posts: 450
Matt, could you please tell us your qualifications that make any of the stuff you write credible? The mere fact that you write about "a critical path" when generally in a digital chip there is exactly one critical path seems to indicate that you are, well, "self-taught". I have a PhD in microelectronics and am a professional microchip developer. What you write is nonsense but will probably impress some gullible people. Well, so be it, I cannot spend as much time as you on writing long-winded technical arguments that most people wouldn't understand anyway.
Originally Posted by matthey View Post
This may be acceptable for an FPGA given the restrictions but is not competitive in an ASIC and the ISA does not allow to grow into something more modern and compatible like the following.

68k compatible superscalar in order integer units, 256 bit partially AVX compatible SIMD unit with integer and floating point support, mostly 68k compatible FPU, MMU with virtual addressing and a compatibility layer for the 68040 and 68060 MMU
Then go and build that.
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