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Old 21 June 2017, 02:05   #87
Join Date: Jan 2010
Location: Kansas
Posts: 1,284
Originally Posted by modrobert View Post
Think I understand what you are getting at, correct me if I'm wrong.

By avoiding FPGA vendor primitives and focusing on implementing all in plain VHDL/Verilog you open the door to future ASIC masks which potentially can give at least ten times the performance of the FPGA used now.

Then we are talking GHz range in performance, having 68k up there with modern PPC in performance, perhaps even surpass. I can relate to this dream and understand your concerns.
Your understanding is close. The worst choices are ISA choices which greatly restrict compatibility now and future choices (like in an ASIC). Some examples.

Apollo ISA: 64 bit integer unit registers are shared with 64 bit SIMD unit registers in the ISA
Reason: resources worked out nicely in the current Altera FPGA
Result: 128, 256, or 512 bit SIMD unit registers would give 128, 256 or 512 bit wide integer unit registers slowing down a critical path
Result: floating point in the SIMD unit would give floating point in the integer unit registers slowing down a critical path
Result: no floating point in the SIMD unit means the FPU needs to become a vector FPU (a floating point SIMD unit) and the 68k FPU deprecated (no backward compatibility) because it is not a good candidate to turn into a vector unit
Result: integer units receive only partial and non-orthogonal 64 bit support which give little advantage especially for compilers
Result: integer units have a large register file which is less energy efficient and the SIMD unit can not be gated (turned off) to save energy when not in use as is common for an SIMD unit

Apollo ISA: 80 bit 68k FPU should be replaced with 64 bit floating point vector FPU
Reason: there is no 67 bit barrel shifter in the current Altera FPGA for normalization so too slow in FPGA
Result: no compatibility with the 68k FPU

Apollo ISA: an MMU with virtual addressing is too slow in an FPGA
Reason: no room or resources for a fancy MMU in an FPGA
Result: no 68k compatible MMU layer, no 68k version of PAE, no virtual memory, etc.

Gunnar and grond think someone would make an ASIC out of the Apollo Core with the following features.

68k compatible superscalar in order 64 bit integer units, 64 bit partially MMX compatible integer only SIMD unit, vector FPU supporting single and double floating point, basic MPU unit

This may be acceptable for an FPGA given the restrictions but is not competitive in an ASIC and the ISA does not allow to grow into something more modern and compatible like the following.

68k compatible superscalar in order integer units, 256 bit partially AVX compatible SIMD unit with integer and floating point support, mostly 68k compatible FPU, MMU with virtual addressing and a compatibility layer for the 68040 and 68060 MMU

Originally Posted by emufan View Post
can anyone attache the image from the a1k post:
The HDMI was a cheap but good hack (almost free hardware cost). I asked if it was possible to drive DVI/HDMI from the FPGA without SerDes and was pleased to find that it was. I may have been the first to ask if AGA could be implemented with it but that was relatively unknown at the time. As long as it doesn't damage any hardware then the HDMI implementation is a success IMO. The AGA on an ECS machine is awesome too but they should make a way to disable it.

Last edited by matthey; 21 June 2017 at 15:23.
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