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Old 20 June 2017, 22:38   #81
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Join Date: Jun 2015
Location: Germany
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Originally Posted by modrobert View Post
By avoiding FPGA vendor primitives and focusing on implementing all in plain VHDL/Verilog you open the door to future ASIC masks which potentially can give at least ten times the performance of the FPGA used now.
Nonsense. An ASIC also uses "primitives". There is nothing to be avoided. Look at it like this: there is this guy that writes a lot in forums how cool bis ideas are. And then there is this other guy who has actually implemented not only a very fast 68k but who also took part in the development of IBM's POWER8 CPU and more recently of a 64bit ARM processor.
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