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Old 29 May 2017, 11:56   #7
Toffee
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Join Date: Sep 2008
Location: Farnborough
Posts: 111
A few high level specifications from the documents (a few conflicts with Wikipedia).

2 chip system sub $40 cost (0.6 micron).
  • CPU/Renderer 64 bit Chip (Nathaniel)
    • HP PA RISC (64 bit)
      • Operates using 50mhz clock (guess-timate) performance of 55 VAXMIPS.
      • Integer only
      • 5 stage pipeline
      • Instruction / Data cache
      • MMU
      • SFU instructions added
    • Audio
      • 12 AAA style 16 bit 44.1 khz CD quality channels
    • Copper
      • 64 bit
      • Move multiple
      • No horizontal waiting
      • Move, Wait and Jump instructions
    • Blitter
      • 64 bit
      • Regular blits, line draw, shaded fills and texture mapping (quads/fixed point)
      • Clipping
      • Shadow registers
      • Pixel addressed (Supports 8, 16 and 32 bit colour)
      • 3 sources
    • Memory Copier
      • Memory to memory copy/fill
      • Consider it an independent simple minded Blitter channel
  • Video Chip (Natalie)
    • Horizontal resolutions 640, 800, 1024 and 1280 (no 320 ?)
    • Vertical up-to 1024
    • 8 bit palette, HAM8, 16 and 32 bit chunky colour modes (In 32 bit mode its 24 bit colour + 8 bit overlay)
    • 2 * 256 24 bit CLUTs
    • 4 playfields (each upto 8 bit, combined = 32 bit mode)
    • Each playfield can be scrolled, scaled and positioned
    • Hardware playfield scaling ranges from 0.5 to 16x
    • Architecture supports 16 sprite channels (only 8 implemented) with 8 bit colour and 128 pixels wide. Sprites can be scaled or repeated. (Later document seems to mostly drop sprites)

Last edited by Toffee; 29 May 2017 at 12:26.
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