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Old 01 January 2017, 03:45   #15
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Location: Glasgow
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Originally Posted by whiteb View Post
Does the 68030 / 68882 need any special instructions (say in Verilog or CPLD) to make it available at system init ?
From what I can tell we simply assert the chip select during the correct CPU SPACE cycle. I have used a 32 bit wide bus.. i wonder if that actually causes issues.
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