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Old 22 November 2016, 11:49   #27
spidi
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Join Date: Jan 2014
Location: Wroclaw/Poland
Posts: 114
Quote:
Originally Posted by Schoenfeld View Post
Spidi,

your sync design gets every single cycle, that's excellent. From what I can see on the pictures, you should have the possibility to add a MapROM function, this will give you quite some extra speed on Sysinfo stones and IDE performance (unless you run a patched scsi.device that's already in fastmem - then you already have the best speed).

At this point, the ACA500plus (which is async, so loses a cycle here and there) beats your sync design just because of MapROM at 14MHz. You can beat the ACA500plus at 14MHz if you implement MapROM. However, you won't reach the ACA500plus speed if it's clocked at 21MHz or more :-)

Jens

Thanks for the advice.
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