View Single Post
Old 21 November 2016, 15:33   #15
Schoenfeld
electricky.
 
Join Date: Jun 2010
Location: out in the wild
Posts: 1,238
Spidi,

your sync design gets every single cycle, that's excellent. From what I can see on the pictures, you should have the possibility to add a MapROM function, this will give you quite some extra speed on Sysinfo stones and IDE performance (unless you run a patched scsi.device that's already in fastmem - then you already have the best speed).

At this point, the ACA500plus (which is async, so loses a cycle here and there) beats your sync design just because of MapROM at 14MHz. You can beat the ACA500plus at 14MHz if you implement MapROM. However, you won't reach the ACA500plus speed if it's clocked at 21MHz or more :-)

Jens
Schoenfeld is offline  
 
Page generated in 0.04661 seconds with 9 queries