Originally Posted by Schoenfeld
I've thought about overclocking, especially because my PLL will generate a clean clock up to 80MHz (so 40MHz CPU clock in theory), but I'm afraid of capacitive load and rise/fall times being too slow to work reliably. I am therefore developing this with a standard 25MHz clock (50MHz memory clock) and will only guarantee proper function that speed. Anything faster than that is "free bonus"; if it works for a specific setup: Good for you. If it doesn't: Please reduce the clock rate.
Most A2630 owners will be limited to 28-30 MHz if they want to try overclocking (and I already warned them it will take a huge amount of work to go beyond that and be very risky unless they really know what they are doing). So your Big RAM 2630 probably has enough timing margin for a little overclocking.
I know the capacitance load issue is the main issue on the Big RAM side of the expansion port but on the A2630 side the resistor load issue is really a bigger problem (especially for the address and data buses). There are also some skew problems on the Clocks, logic arbitration delay problems, etc.
The DKB2632 originally used 74F244s for it's address buffers which place a full TTL load on the address bus. The problem is the Address bus was already overloaded (especially after the FCC guys switched the 1K pull downs to pull ups)... and there is much much more!
It's truly amazing that with all the design bugs this combination worked as well as it did!