Originally Posted by eXeler0
Yes, but a CPU that can execute 2 instructions per clock cycle is not measured fairly if the MIPS are for code running on only one pipeline.
Theoretically, a 50MHz 060 could have 100MIPS if we toy with the idea that every instruction can be executed in one cycle. But only if both pipelines are fully fed.
Dhrystone MIPS are measured with some fairly simple C algorithms. Compilers can produce optimal code for superscalar processors like the 68060 and Apollo core but they generally don't for the 68k. Dhrystone MIPS ends up measuring the compiler optimization capabilities. The compiled code can be hand tweaked following the rules for Dhrystone which makes a huge difference but some would say that is cheating. Using the Dhrystone MIPS algorithm makes sense but then the decision of which resulting executable to use is not so simple. Of course anything would be better than the old SysInfo speed test which doesn't even use common instructions.