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Old 24 June 2003, 05:41   #15
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Join Date: Aug 2001
Location: Connecticut USA
Posts: 543
Originally posted by Twistin'Ghost
And I never considered the 68000's clock speed having to be divisible by the blitter!
only because Commodore chose to use a synchronous cpu/custom chip clock design. they clocked everything from the 28.XXXX mhz crystal, divided it by 4 for the cpu, divided it by 40 for the PIA's (8520's), and divided it by 8 for the custom chipset (including Denise video output). If they wanted NTSC timings they used one crystal, if it was a PAL machine they used a slightly slower crystal.

grrr, I'm trying to remember if the custom chips were clocked at 7 or 3.5mhz. something is telling me that everything on the RGA bus (paula/denise/agnus) was 3.5mhz, not just Denise. haven't looked at the schematics in 10 years. something about the 68000 typically only wanting to access memory every other clock cycle.

the upshot is that a PAL display mode generated by an NTSC machine isn't quite exactly PAL, and an NTSC display generated by a PAL machine isn't quite NTSC (because the crystal frequency is wrong). but they're pretty close.

of course back then everyone did synchronous chipset designs (it was cheaper than an asynchronous design), zorro-3 was the first real break from that (at least for the expansion bus).
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