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Old 02 February 2016, 23:26   #33
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Join Date: Jan 2010
Location: Kansas
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Originally Posted by Mrs Beanbag View Post
the way i like to think about the Blitter is as a single cell of a dynamically-programmable FPGA connected to a DMA channel. It is basically a really simple stream processor. The logical progression, to my mind, is to simply have lots of them (with maybe some boosted functionality), able to run in parallel or maybe even in series.
Parallel blitters would have been good for 256 color planar graphics but it would be a waste of resources now that even FPGA hardware has enough bandwidth for moderate to high resolution in at least 16 bit chunky. The way to work on chunky is with SIMD. One proposal for problems with a high speed blitter was to trap to the CPU/SIMD which would handle the work. A more versatile and standard SIMD would allow other code to be accelerated also. Grond hinted at this being used by SAGA/Apollo which I believe to be true if and when it is possible.
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