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Old 26 November 2015, 18:40   #37
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Originally Posted by jbenam View Post
That's because Jens has clearly stated he'll never make one
He isn't against FPGAs

Originally Posted by Schoenfeld View Post
...The next step would be to work with faster CPLDs (or an FPGA) and have another go at 100MHz (or more) system clock. The whole magic is in generating the right clock phases and reading the SD-Ram datasheets between the lines :-)Jens
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