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Old 25 November 2015, 18:34   #18
Join Date: Jun 2010
Location: out in the wild
Posts: 1,251
Originally Posted by esc View Post
I'm interested in learning more about the SD-RAM controller. How is this different from past methods?
Previously, the SD-Ram was clocked at twice the CPU speed. This would have required 100MHz ram clock, which is instable with the 10ns CPLDs. Further, at 100MHz, the setup and hold times of the old 68030 CPU cannot be met: 4.5ns setup before clock and 7.5ns hold after clock were only met with a trick on the 40MHz cards, but can't be met at 100MHz ram clock using the current ACA1232/1233 wiring.

The new controller works at the same speed as the CPU clock - that's the main difference.

Originally Posted by esc View Post
What benefit does this have now?
It works reliably :-) Seriously, there are a few people who took the ACA1232 and overclocked it to 100MHz system clock, resulting in 50MHz CPU clock. Such a card is pretty fast (faster than the new cards I'm currently offering), but it's instable - it crashes after a few minutes warm-up time. Most of the customers who did that have sent me mails about going back to 80MHz system clock, which is the highest stable clock with the previous design.

Originally Posted by esc View Post
And is this something that you will be utilizing in future accelerators as well?
Kind of. The next step would be to work with faster CPLDs (or an FPGA) and have another go at 100MHz (or more) system clock. The whole magic is in generating the right clock phases and reading the SD-Ram datasheets between the lines :-)

Originally Posted by Bester View Post
Just ordered one, order ID 10000 at (hopefully I get a chocolate for that ).
Yep, seen the order - thanks. I think there is one "please pardon the inconvenience"-chocolate left from the C64 Reloaded update-round (that was before you got yours).

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