Perhaps the most realistic (still very unrealistic!) way to get to make an ASIC to improve 68k performance would be making a special-purpose FPGA? Making it open-source perhaps could build enough interest from people that it actually could be manufactured...
What I'm thinking of is a FPGA where:
. large memory blocks having dedicated interconnects to build caches.
. small memory blocks either have direct support for multiple writes or dedicated hardware to emulate multiple write ports (for register files).
. ALU blocks that supports add/sub/logical/shift operations, SIMD splitting etc.
. support for result bypassing.
. multiplier blocks suitable for SIMD execution, dedicated logic to build larger multipliers and direct support for signed/unsigned multiplications.
. CAM (Content Addressed Memory) support.
. Signal routing specialized for larger buses.
This would be less dense than a normal FPGA but for things that match the architecture the result could be impressive.
Alternatively it could be even more hardwired for processor applications, something like a processor with some programmable hardware to support decoding + architectural quirks.