Originally Posted by Megol
One less option :/
Perhaps eASIC could be an alternative? Don't know how easy it is to port from Altera. http://www.easic.com/
Maybe so. The current Apollo Team softcore is written in VHDL though the consumer-grade Altera Cyclone 4 FPGAs will only clock the core up to roughly 133 MHz. (At least that's enough to outrun a 68060 by a long shot bringing feasibility to future development.)
Beating an ASIC with an FPGA is difficult. I estimated that a 500-600 MHz core based on 68k would be enough to wipe the floor with my PPC 750FX at 800 MHz due to RISC core inefficiency associated with the Load/Store architecture. Since the PPC doesn't use opcode fusion like the Apollo core, the FPGA might catch up with lower clock speeds than even 400 MHz!
Using a modular eASIC-style ASIC could get the speed up to what we need if the demand is high enough. Some obstacles are that the core has to be debugged first. Also, since the Apollo core drops some 68k functions that are not legal to use on the Amiga chipset systems, the chip would need to be an SoC with its AGA++ core integrated to make the expense worthwhile of doing the die layout. (The reason I think that is the case is because the Apollo core is only user-mode ISA compatible with 68k. There are other 68k systems that it won't work with.)
IF that all happens, it'll be interesting to see how it stacks up against the PPC and more importantly, how well the AGA++ core can mop the floor with an older Radeon card. My MicroA1 has a Radeon 7000 chip on the motherboard and it isn't upgradable. (If the AGA++ graphics core can go far enough to compete with my sister's old Radeon X700, I'll probably ditch PPC for good! The PPC already can't keep up with my Core2 Duo-based Mac.)