Originally Posted by Schoenfeld
The P1022 is a dual-core CPU. Even if you were to emulate all FPU commands in software, you'd have a spare core to do that, as OS4 is still a single-core OS.
Have you ever tried something like that? The synchronization overheads would be extreme unless there is special hardware support for it, it would be faster emulating it in the main core.
Besides, it's not all-incompatible, but throws a few illegal instruction traps on commands not implemented (according to one of the developers I talked to last saturday). That's about the same as what the 060 CPU does for unimplemented commands of the earlier members of the 68k group. Would you make fun of those who designed with the 060 back then? Surely not.
The e500v2 core uses a special instruction set: SPE (which BTW makes it impossible to support Altivec on a follow-up core as the instruction encodings overlap) which uses the main register file for floating point data.
It should be obvious to anyone who have done something remotely similar that emulating a standard FPU with such a system would be dog slow, not only do one need to trap instructions one also need to swap register values around to emulate the FP registers.
Sure, with a lot of effort one could use a binary translation approach to increase performance - but then one could use an x86 core instead and get much better performance for a lower cost.
And the price? Incredible. Why not make an effort to make a good PPC emulator for a standard PC instead?
Edit: "skilled in the arts" changed - I've read to many patents lately :/)