Originally Posted by pandy71
Just buffer/interleave R/W - should be fine - 8ns access is way above 100MHz so with proper cycling You should be able to fit in this perfectly.
And yes - output easily can be pixel doubling/quadrupling + max size is not full 1920 line period and as such you can use part of time for other thing (and mask with fixed color) - it will create some pilarbox but i believe this is unavoidable if you think about pixel perfect Amiga screen replication on modern 16:9 FHD TV's (pilarbox can be removed in TV when this mode will be selected and trough correct signaling and usually TV will provide better scaler than FPGA can have without going to expensive one, also you can use own timing but it is different case).
It is a little more complex. The output clock for 720p is 74.25Mhz, it means that you will need to clock some function/statemachine in FPGA that will read SRAM and that will use a multiple of this frequency. The FPGA that I am using cannot operate at multiple of 4 (297Mhz) with current implementation, only 2 (148,5Mhz) is possible, thus the granularity for the FPGA statemachine is not fine. This in combination with constraints for the SRAM when it comes to signalling makes me unable to use whole bandwidth of SRAM.