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Old 26 April 2015, 22:07   #66
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Join Date: Dec 2013
Location: Lake Havasu City, AZ
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Originally Posted by Megol View Post
Let's assume the shifter in a one stage implementation requires 8ns worst case, then the maximum clock rate is 125MHz.
But one can split the shifter into a two pipeline stage design and then one could perhaps have a 4ns latency per stage enabling 250MHz.
One can't separate the latency of operations and the clock rate - they are expressions of the same thing: frequency=1/latency, latency=1/frequency
I am talking about clocking the entire FPGA itself at a higher clock rate, using a newer part that can be clocked at a higher rate.
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