Originally Posted by JimDrew
If you have a base clock of 50MHz and change that base clock to 250MHz, you would see a 5x speed increase, no? Faster part = faster speed.
Let's assume the shifter in a one stage implementation requires 8ns worst case, then the maximum clock rate is 125MHz.
But one can split the shifter into a two pipeline stage design and then one could perhaps have a 4ns latency per stage enabling 250MHz.
One can't separate the latency of operations and the clock rate - they are expressions of the same thing: frequency=1/latency, latency=1/frequency