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Old 25 April 2015, 18:48   #60
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Join Date: Dec 2013
Location: Lake Havasu City, AZ
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Originally Posted by Megol View Post
What? The reason one use multiple cycles (in a pipelined design) is to enable a higher clock rate.
One can't separate the logic latency from the clock rate.
If you have a base clock of 50MHz and change that base clock to 250MHz, you would see a 5x speed increase, no? Faster part = faster speed.
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