View Single Post
Old 25 April 2015, 13:30   #58
Registered User

Megol's Avatar
Join Date: May 2014
Location: inside the emulator
Posts: 304
Originally Posted by JimDrew View Post
I am not an FPGA guru, but the solution for having to use multiple cycles (if that is really necessary) is using a faster base clock for you logic.
What? The reason one use multiple cycles (in a pipelined design) is to enable a higher clock rate.
One can't separate the logic latency from the clock rate.
Megol is offline  
Page generated in 0.03912 seconds with 10 queries