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Old 25 April 2015, 13:30   #58
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Join Date: May 2014
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Originally Posted by JimDrew View Post
I am not an FPGA guru, but the solution for having to use multiple cycles (if that is really necessary) is using a faster base clock for you logic.
What? The reason one use multiple cycles (in a pipelined design) is to enable a higher clock rate.
One can't separate the logic latency from the clock rate.
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