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Old 02 April 2015, 01:40   #14
Join Date: Jan 2010
Location: Kansas
Posts: 1,284
Originally Posted by alexh View Post
A bit of synical conclusion don't you think?
It's the truth even if it sounds cynical.

Originally Posted by chaos View Post

I'm the person working on the minimig AGA core for the mist board.

There seems to be a lot of speculation about this, so a few words from the horse's mouth, as they say

- You can find all the work I've done on the minimig core for the DE1 board and later on the MIST on github, starting on 3. Dec 2011:
As you can see, I'm not exactly new at minimig
That's a lot of commits. You have obviously done a lot of work and you know what you are doing. I am always impressed when I find experts in jobs I didn't know existed a few years ago. I wish Amiga software development progressed as quickly .

Originally Posted by chaos View Post
- Yes, my minimig AGA core was written pretty fast, the majority in a week of sick leave actually You'd be surprised how little changes AGA requires on top of ECS. It is of course based on minimig ECS, which thanks to everyone working on it, especially yaqube, is a great place to start There is also the AGA guide document, which describes all the added / changed custom registers of the AGA chipset. You can implement around 75% of AGA on top of ECS and still be completely ECS compatible, which makes testing it (With small ASM-one few-liner programs) very easy. Of course, once you switch Lisa ID, all hell breaks loose Here is the approximate sequence how I did it:
* convert the minimig core to a single 28MHz clock (not absolutely neccessary, but I didn't know that at the time)
* check if SDRAM controller implementation is good enough for 64-bit DMA fetches (it was) and add 64bit data paths for sprite and bitplane data
* implement AGA color LUTs, converting the LUT to blockrams, fix HAM6, HAM8 & EHB modes
* implement dither for video output, as the MIST only supports 18-bit output
* implement new bitplane DMA sequencer, bitplane modulos etc - I spent most of the time on this
* add / fix 64-bit serializer regs for bitplane data and fix sprite serializer implementation
* than you can start incrementally adding bits from new AGA registers and testing as you go, like border sprites, color table XOR, color table offsets, ...
* keep in mind that the most complex parts of the chipset - the blitter and copper - aren't changed AT ALL!
Interesting. You make it sound easy. I take it you were already familiar with the Amiga and 68k which probably helped.

Originally Posted by chaos View Post
Most of this can be done with the help of the existing minimig ECS codebase, the AGA guide document, and common sense, especially thinking about how they upgraded the ECS chipset with minimal changes and in a compatible way. And, of course, with A LOT of guessing
And, if you are wondering, yes, I am (well, was) a professional ASIC designer, so you could say I have some idea what I'm doing. I also had some help from Toni Wilen, who nudged me in the right direction.
I have the AGA guide but I never got into programming the Amiga custom chips despite being a 68k assembler programmer. Toni knows more than any book. He should write an AGA hardware guide.

Originally Posted by chaos View Post
The AGA core is also not complete, not by far. There are some missing features waiting to be implemented, like bitplane / sprite scandoubling, programmable display modes are missing (they are missing from minimig ECS also), the bitplane scroll is wrong for some modes, border sprites are not always correct, the CPU only has a 16-bit bus, ... And of course, the hardest part - finding a million corner cases which are currently not handled properly.

Yes, I'd prefer if yaqube's AGA updates were made available, I was waiting for that for how many years now since it was first announced? At some point, I just decided to do it myself ...
I think the FPGA Arcade updates will be released if the FPGA Arcade comes out before it's outdated. Having the HDL code for both AGA cores available should accelerate development.

Originally Posted by eXeler0 View Post
Rok, have you talked to MikeJ @ FPGA Arcade? The tiny 68k Amiga world that is left could use some co-operation ;-)
The Mist guys seem to be more open. Maybe the FPGA Arcade guys are just too busy .

It would be good to have some cooperation on an enhanced AGA+RTG (with Chunky) and RTA standard. Unfortunately, the guys in charge of the Mist and FPGA Arcade projects only seem to want legacy compatibility with minimal bolt-ons. Gunnar of the Apollo/Phoenix project doesn't care about an enhanced Amiga chip set standard either unless they are optimized for his implementation and he can define them (maybe Marcel "Veda" Verdassdonk and Thomas Hirsch would be more open). I tried to create an enhanced standard 68k ISA but Gunnar made his own which I don't think any 68k FPGA CPU would or easily could follow. More division and chaos in the Amiga community seems to be par .
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