Originally Posted by matthey
I have no insider knowledge on this so everything I said is hearsay based on what I have read. The Mist AGA core became available and usable very quickly considering there is limited hardware information about AGA (no AGA Hardware Reference Manual like for ECS). Look at the effort to reverse engineer and document the Amiga chipset with Clone-A and even hooking a 1200 up to analysers currently for the FPGA Arcade. Granted, there have been stealth projects like the AGA MiniMig and Natami which did a lot of work under the radar before surprising us with how far they had progressed. Either someone really knew what they were doing with Mist AGA or they had more than a peak at some version of the MiniMig AGA core.
I'm the person working on the minimig AGA core for the mist board.
There seems to be a lot of speculation about this, so a few words from the horse's mouth, as they say
- You can find all the work I've done on the minimig core for the DE1 board and later on the MIST on github, starting on 3. Dec 2011:
As you can see, I'm not exactly new at minimig
- There has been (almost) NO code sharing between either the FPGAArcade team or the yaqube's new minimig AGA core and me. Mike did send an updated TG68K CPU core with some changes to Till Harbaum, who forwarded it to me, but that is it.
- Yes, my minimig AGA core was written pretty fast, the majority in a week of sick leave actually
You'd be surprised how little changes AGA requires on top of ECS. It is of course based on minimig ECS, which thanks to everyone working on it, especially yaqube, is a great place to start
There is also the AGA guide document, which describes all the added / changed custom registers of the AGA chipset. You can implement around 75% of AGA on top of ECS and still be completely ECS compatible, which makes testing it (With small ASM-one few-liner programs) very easy. Of course, once you switch Lisa ID, all hell breaks loose
Here is the approximate sequence how I did it:
* convert the minimig core to a single 28MHz clock (not absolutely neccessary, but I didn't know that at the time)
* check if SDRAM controller implementation is good enough for 64-bit DMA fetches (it was) and add 64bit data paths for sprite and bitplane data
* implement AGA color LUTs, converting the LUT to blockrams, fix HAM6, HAM8 & EHB modes
* implement dither for video output, as the MIST only supports 18-bit output
* implement new bitplane DMA sequencer, bitplane modulos etc - I spent most of the time on this
* add / fix 64-bit serializer regs for bitplane data and fix sprite serializer implementation
* than you can start incrementally adding bits from new AGA registers and testing as you go, like border sprites, color table XOR, color table offsets, ...
* keep in mind that the most complex parts of the chipset - the blitter and copper - aren't changed AT ALL!
Most of this can be done with the help of the existing minimig ECS codebase, the AGA guide document, and common sense, especially thinking about how they upgraded the ECS chipset with minimal changes and in a compatible way. And, of course, with A LOT of guessing
And, if you are wondering, yes, I am (well, was) a professional ASIC designer, so you could say I have some idea what I'm doing. I also had some help from Toni Wilen, who nudged me in the right direction.
The AGA core is also not complete, not by far. There are some missing features waiting to be implemented, like bitplane / sprite scandoubling, programmable display modes are missing (they are missing from minimig ECS also), the bitplane scroll is wrong for some modes, border sprites are not always correct, the CPU only has a 16-bit bus, ... And of course, the hardest part - finding a million corner cases which are currently not handled properly.
Yes, I'd prefer if yaqube's AGA updates were made available, I was waiting for that for how many years now since it was first annnounced? At some point, I just decided to do it myself ...