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Search: Posts Made By: PiCiJi
Forum: Coders. Asm / Hardware 01 August 2017, 20:14
Replies: 15
Views: 3,653
Posted By PiCiJi
seems the cia chips were more designed for the...

seems the cia chips were more designed for the c64. I have read the c64 can access the cia faster than amiga in a 6510 half cycle
Forum: Coders. Asm / Hardware 28 July 2017, 18:59
Replies: 15
Views: 3,653
Posted By PiCiJi
data transfer happens during 4 high cycles ,...

data transfer happens during 4 high cycles , followed by 6 lo cycles 4 + 6 = 1 e-clock

Why is the cpu waiting additional 6 cycles ... because of misaligning of cia and cpu (6 cycles worst)
Or if...
Forum: Coders. Asm / Hardware 06 January 2017, 20:50
Replies: 28
Views: 7,625
Posted By PiCiJi
M68000 user manual ninth edition: The...

M68000 user manual ninth edition:

The transition from supervisor to user mode can be
accomplished by any of four instructions: return from exception
(RTE) (MC68010 only), move to status register...
Forum: Coders. Asm / Hardware 21 October 2016, 20:36
Replies: 28
Views: 7,625
Posted By PiCiJi
thanks for information folks

thanks for information folks
Forum: Coders. Asm / Hardware 19 October 2016, 20:30
Replies: 28
Views: 7,625
Posted By PiCiJi
For emulating the 68020 it’s hard to calculate...

For emulating the 68020 it’s hard to calculate the right amount of internal cycles between bus cycles, because of the non hardcoded design. The correct placement of bus cycles matters so that other...
Forum: Coders. Asm / Hardware 16 October 2016, 15:14
Replies: 28
Views: 7,625
Posted By PiCiJi
Thanks for clarity. I am trying to...

Thanks for clarity.

I am trying to understand prefetches for 68020.

It says a memory access costs 3 cycles. It seems a long word access is one bus cycle instead of 2 like the 68000.

a few...
Forum: Coders. Asm / Hardware 16 October 2016, 13:56
Replies: 28
Views: 7,625
Posted By PiCiJi
seems true for immediate and register ASL,...

seems true for immediate and register ASL, because sequence describes shifting after prefetch

ASL (An)

sequence: nr (read from An), np (prefetch), nw (write shifted result)
shifting and...
Forum: Coders. Asm / Hardware 14 October 2016, 20:12
Replies: 28
Views: 7,625
Posted By PiCiJi
68k timing

last time I have thought about 68k timing again.

Whats happening with internal operation during wait states ?

e.g. ASL Dx, Dy
sequence: prefetch n* n (* means shift count, n -> 2 cycles,...
Forum: support.Hardware 26 November 2015, 17:50
Replies: 4
Views: 736
Posted By PiCiJi
saving high scores or savegames, not copying...

saving high scores or savegames, not copying protected games. The real amiga disk drive can read with a variable bit length but write with a fixed bit length only. I don't expect more features from a...
Forum: support.Hardware 26 November 2015, 14:45
Replies: 4
Views: 736
Posted By PiCiJi
Sure ? ...

Sure ?

http://hxc2001.free.fr/floppy_drive_emulator/index.html#USBFloppyemulator
Forum: support.Hardware 26 November 2015, 13:22
Replies: 4
Views: 736
Posted By PiCiJi
floppy emulator ipf + write support?

Im interested in floppy drive emulators and I read about the HxC.
The SD card version has write support but no support for reading variable bit rate (ipf images).
The usb version is read only but...
Forum: support.Hardware 16 September 2015, 20:27
Replies: 8
Views: 898
Posted By PiCiJi
I think so too.

I think so too.
Forum: support.Hardware 16 September 2015, 18:26
Replies: 8
Views: 898
Posted By PiCiJi
a500 kick 1.3 autoboot from hd in command line

back in days I had an A500+ with hd. When playing Monkey Island 2 from hd with 1 MB chip mem there are strange problems like slowdowns because of too little memory. I could solve it by using the kick...
Forum: support.Games 26 August 2014, 11:26
Replies: 17
Views: 5,780
Posted By PiCiJi
in hol there is an "enhance" hardware category. I...

in hol there is an "enhance" hardware category. I would understand it as OCS agnus is not enough to play these games. Maybe both games should be listed there?
Forum: Coders. Asm / Hardware 17 August 2014, 19:19
Replies: 11
Views: 3,294
Posted By PiCiJi
ok I would assume if plane is enabled in clxcon...

ok I would assume if plane is enabled in clxcon but disabled in bplcon0, 0 is compared with the "match" value.

and i would assume if even planes are already shifting and odd planes still delayed...
Forum: support.Games 17 August 2014, 18:18
Replies: 17
Views: 5,780
Posted By PiCiJi
How much ECS features use the games Wasted Dreams...

How much ECS features use the games Wasted Dreams and Hell Squad ? Is it only the agnus ecs feature to handle 2 MB chipram or are there ecs denise features in use ? I wonder if the graphics differ...
Forum: Coders. Asm / Hardware 01 August 2014, 22:32
Replies: 239
Views: 160,809
Posted By PiCiJi
very interesting, I have thought the delay is...

very interesting, I have thought the delay is processed only at the beginning of first scanline fetch and following playfield data is added to some ring buffer.
I assume in single playfield mode the...
Forum: Coders. Asm / Hardware 31 July 2014, 23:17
Replies: 15
Views: 3,172
Posted By PiCiJi
In HRM the one pixel delay after bitplane fetch...

In HRM the one pixel delay after bitplane fetch seems to be considered for hdiw, but the sprite is 1 pixel too late or the hdiw is 1 pixel too soon.



Only 1 pixel? I thought an early opened...
Forum: Coders. Asm / Hardware 30 July 2014, 21:10
Replies: 15
Views: 3,172
Posted By PiCiJi
yes HRM doesn't mention any offset between sprite...

yes HRM doesn't mention any offset between sprite x and hdiwstrt. By reading HRM I get the impression that there shouldn't any offset.
Forum: Coders. Asm / Hardware 29 July 2014, 22:05
Replies: 15
Views: 3,172
Posted By PiCiJi
the -1 part is strange. means when hdiwstart ==...

the -1 part is strange. means when hdiwstart == xSprite, then the first sprite pixel is one pixel ahead of left border ?

edit: maybe after successfull sprite x position comparison the sprite can...
Forum: Coders. Asm / Hardware 06 July 2014, 16:33
Replies: 11
Views: 3,294
Posted By PiCiJi
OCS collision and clx registers

it seems collision detection isn't documented that well. I have a few understanding questions.

CLXCON bits 11 - 0: Have these bits any influence to sprite collisions or is it considered for...
Forum: Coders. Asm / Hardware 05 July 2014, 10:54
Replies: 9
Views: 2,542
Posted By PiCiJi
I have found some info in following document: ...

I have found some info in following document:
http://palbo.dk/dataskolen/maskinsprog/english/letter_04.pdf

it reads:
Remember that if DDFSTRT does not end with $0 or $8 then it is rounded down...
Forum: support.Games 15 June 2014, 20:03
Replies: 26
Views: 3,415
Posted By PiCiJi
means the game is generating the 3D environment...

means the game is generating the 3D environment with the blitter for a plain A500? interesting
Forum: support.Games 12 June 2014, 21:01
Replies: 26
Views: 3,415
Posted By PiCiJi
good to know. I wonder if the game needs 020...

good to know. I wonder if the game needs 020 instructions for generating floor/ceiling textures. If not, I wouldn't understand why a higher clocked 68000 is not supported.
By the way what was the...
Forum: support.Games 12 June 2014, 18:22
Replies: 26
Views: 3,415
Posted By PiCiJi
I am not sure if WinUAE can emulate a turbo card...

I am not sure if WinUAE can emulate a turbo card appropriately. From memory, I think I have tried it in WinUAE (doubling 68000 speed) without success.
Forum: support.Games 12 June 2014, 18:03
Replies: 26
Views: 3,415
Posted By PiCiJi
What I always wanted to know, is it possible to...

What I always wanted to know, is it possible to activate floor/ceiling with A500 + 68000 turbo card ?
I wonder if the game checks if 68020 instructions are present to decide if floor/ceiling is...
Forum: Coders. Asm / Hardware 26 August 2013, 19:56
Replies: 9
Views: 2,964
Posted By PiCiJi
good to know. Could be interesting what happens...

good to know. Could be interesting what happens by changing the vertical DIW midline and disable the currently rendered line.
Forum: Coders. Asm / Hardware 25 August 2013, 19:21
Replies: 9
Views: 2,964
Posted By PiCiJi
Yes I know that DIW is independent from DDF for...

Yes I know that DIW is independent from DDF for left/right clipping. I would suppose it behaves the same for top/bottom clipping?

So reducing the display height doesn't disable DDF fetch for non...
Forum: Coders. Asm / Hardware 06 July 2013, 20:14
Replies: 9
Views: 2,964
Posted By PiCiJi
Thanks yes a typo.

Thanks



yes a typo.
Forum: Coders. Asm / Hardware 06 July 2013, 18:15
Replies: 9
Views: 2,964
Posted By PiCiJi
I have read the whole playfield chapter again. I...

I have read the whole playfield chapter again. I am sure the bitplane fetch is related to screen position.

typical: 320 pixel
diw: 0x81 <-> 0xc1 (0x1c1)
ddf: 0x38 <-> D0(D7)

max: 368 pixel...
Forum: Coders. Asm / Hardware 04 July 2013, 21:12
Replies: 9
Views: 2,964
Posted By PiCiJi
relation between diwstrt and ddfstart

I have some problems understanding the relation between diwstrt and ddfstart.

diwstart defines the screen area in use. The outside part is displayed in background color.

ddfstart defines the...
Forum: Coders. Asm / Hardware 26 June 2013, 22:45
Replies: 8
Views: 2,901
Posted By PiCiJi
I haven't taken in account the higher level dma...

I haven't taken in account the higher level dma accesses which can increase cycles between D pointer access and CPU writes during idle cycle. So it should be normal that some pointer changes are...
Forum: Coders. Asm / Hardware 26 June 2013, 22:14
Replies: 8
Views: 2,901
Posted By PiCiJi
word writes only. can blitter idle...

word writes only.



can blitter idle cycles executed during refresh cycles or is it delayed until next free cycle?
Forum: Coders. Asm / Hardware 26 June 2013, 20:04
Replies: 8
Views: 2,901
Posted By PiCiJi
I have tried to change the D pointer during blit...

I have tried to change the D pointer during blit on A500 OCS. Cycle diagram was D only. ( -D )

The results differ between new D pointer is accepted or ignored at all. Blitter nasty or not doesn't...
Forum: Coders. Asm / Hardware 24 June 2013, 19:12
Replies: 239
Views: 160,809
Posted By PiCiJi
in winuae src there is a table with delays for...

in winuae src there is a table with delays for some copper register writes. Can it be considered as hack for something to work?
Forum: Coders. Asm / Hardware 22 June 2013, 18:00
Replies: 239
Views: 160,809
Posted By PiCiJi
Lately I am interested in amiga chipset. ...

Lately I am interested in amiga chipset.



That means the copper move happens in a non Copper cycle (the next bus cycle after the second instruction read) ?

If so, what happens if this cycle...
Forum: Coders. General 20 May 2013, 15:08
Replies: 28
Views: 5,550
Posted By PiCiJi
Thanks Toni. so no bus error can happen on...

Thanks Toni.

so no bus error can happen on A500. I am not sure but the atari can cause bus errors.
Forum: Coders. General 07 April 2013, 21:36
Replies: 28
Views: 5,550
Posted By PiCiJi
Can the amiga cause bus errors? The sega...

Can the amiga cause bus errors?
The sega genesis for example has no device for creating bus errors.

I want to test some instructions with (An)+ or -(An) addressing.

The 68000 doesn't change...
Forum: Coders. General 30 March 2013, 19:27
Replies: 28
Views: 5,550
Posted By PiCiJi
good to know If a result is written to...

good to know


If a result is written to registers most opcodes prefetches with beginning logic cycles. So the last bus cycle of mulu can be a lot of cycles before total instruction time.

In...
Forum: Coders. General 29 March 2013, 10:55
Replies: 28
Views: 5,550
Posted By PiCiJi
neat... The document shows the prefetch times. ...

neat...
The document shows the prefetch times.
For example mulu instruction prefetches at the beginning of logic cycle execution.
Showing results 1 to 40 of 265

 
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