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Search took 0.02 seconds. Search: Posts Made By: FrenchShark
Forum: Amiga scene 22 August 2014, 23:52
Replies: 53
Views: 15,237
Posted By FrenchShark
Hello, just my 2 cents about Cyclone III PLLs. ...

Hello,
just my 2 cents about Cyclone III PLLs.
You can do 28.636363 MHz and 28.375 MHz if you use 5 MHz clock input.
5 x 227 / 40 = 28.375
5 x 252 / 44 = 28.636363
With PLL dynamic...
Forum: Amiga scene 03 July 2014, 22:37
Replies: 245
Views: 56,803
Posted By FrenchShark
Interresting stuff about brigette. In the case...

Interresting stuff about brigette.
In the case of an accelerator + AGA in an FPGA, the whole chip RAM bus and the CPU/Chip bridge is anyway integrated into the FPGA.
Moreover, it is easier to stay...
Forum: Amiga scene 03 July 2014, 22:10
Replies: 245
Views: 56,803
Posted By FrenchShark
2x bandwidth on audio means 58 kHz sampling rate...

2x bandwidth on audio means 58 kHz sampling rate and on disk, direct HD floppy support without the 150 rpm drive hack.
AA Paula would have been useful...

Regards,
Frederic
Forum: Amiga scene 02 July 2014, 23:08
Replies: 245
Views: 56,803
Posted By FrenchShark
On AGA machines, the CPU has 32-bit access to...

On AGA machines, the CPU has 32-bit access to Chip RAM (but still at 3.5 MHz:crying).
But, Paula always does 16-bit access to Chip RAM for Audio and Disk DMAs.

Regards,
Frederic
Forum: Amiga scene 02 July 2014, 23:03
Replies: 245
Views: 56,803
Posted By FrenchShark
I have double checked the A1200 schematics and...

I have double checked the A1200 schematics and the E clock from Gayle seems to be at 700 KHz. The BOM also states "1 MHz VIA 8520".
Hardware docs on internet show that 2 MHz 8520 were only used on...
Forum: Amiga scene 01 July 2014, 23:19
Replies: 245
Views: 56,803
Posted By FrenchShark
If the AGA chipset is put on an FPGA based...

If the AGA chipset is put on an FPGA based accelerator board, 95% of the original OCS/ECS chipset becomes useless (16-bit Chip RAM is too slow for AGA DMAs).
Only the I/O related chips stay a little...
Forum: Amiga scene 01 July 2014, 22:43
Replies: 245
Views: 56,803
Posted By FrenchShark
I did not check the A4000 schematics but CBM/CSG...

I did not check the A4000 schematics but CBM/CSG has released a 2 MHz 8520 and the timer.device on A1200/A4000 Kickstart checks 4 different tick frequencies :
* 50 Hz with 700 KHz E clock,
* 60 Hz...
Forum: Amiga scene 01 July 2014, 22:36
Replies: 245
Views: 56,803
Posted By FrenchShark
IIRC, the DPLL code I posted handles timings...

IIRC, the DPLL code I posted handles timings outside 2us/4us cell size as long as the counter is within CTR_MIN_VAL and CTR_MAX_VAL.
GCR (4us bit cell) is handled with the clock enable, I even added...
Forum: Amiga scene 01 July 2014, 07:42
Replies: 245
Views: 56,803
Posted By FrenchShark
The difficulty with AGA on A500/A2000 are the...

The difficulty with AGA on A500/A2000 are the 8520s that must run at 1.4 MHz. You need at least a small FPGA card to replace the original 8520s (maybe there are 2MHz 8520s in DIL package somewhere...
Forum: Amiga scene 01 July 2014, 07:39
Replies: 245
Views: 56,803
Posted By FrenchShark
Right, the PRECOMP is tricky in the write...

Right, the PRECOMP is tricky in the write support.
GCR is not really used (maybe on some write protected games ? and if you want to read C64 disks ?).
For the DMA, I have a 3-word FIFO and the...
Forum: Amiga scene 01 July 2014, 00:01
Replies: 245
Views: 56,803
Posted By FrenchShark
This is really no big deal. I have done it...

This is really no big deal.
I have done it myself. I am sure Mike had no problem implementing that part.
Here is the DPLL verilog code :-)
Read has been tested. Write, not yet.

// This module...
Forum: Hardware mods 28 June 2013, 23:45
Replies: 3
Views: 2,230
Posted By FrenchShark
Hello, 256 KB Kickstart ROM must be shadowed at...

Hello,
256 KB Kickstart ROM must be shadowed at address F80000 not F00000.
To me, it looks like a wrong address decoding is done by Gary.
IIRC, Gary is responsible of terminating bus accesses on...
Forum: Coders. Tutorials 18 May 2013, 20:44
Replies: 175
Views: 57,519
Posted By FrenchShark
Ok, thanks. There is actually another one in...

Ok, thanks.
There is actually another one in the Disk DMA enable instruction, it should be:
move.w #%1000001000010000,(a0) ;enable disk DMA
Bit #9 has to be set too.

Regards,
...
Forum: Coders. Tutorials 18 May 2013, 11:07
Replies: 175
Views: 57,519
Posted By FrenchShark
Hello, FYI, I am using the trackloader code...

Hello,

FYI, I am using the trackloader code in a verilog testbench to check the correct functionning of Paula / disk emulation.
I think I spotted a bug line 403:
bne.s .time_not_expired
It...
Forum: Coders. Asm / Hardware 22 July 2012, 16:02
Replies: 338
Views: 387,927
Posted By FrenchShark
Did you test the sprite trigger position in NTSC...

Did you test the sprite trigger position in NTSC ?
I am expecting Denise's HPOS to be delayed by half a CCK cycle (one lores pixel) when STRLONG is present. (IMHO, this is the simplest way of...
Forum: Hardware mods 03 December 2011, 21:20
Replies: 736
Views: 159,685
Posted By FrenchShark
Hello, you can ignore A[0], it is just used...

Hello,

you can ignore A[0], it is just used internally by the TG68 to generate uds_n and lds_n :

This is from the TG68 source (lines #402-403 in my file) :

lds_n <= '0' WHEN (datatype/="00"...
Forum: Hardware pics 20 October 2011, 20:31
Replies: 44
Views: 14,652
Posted By FrenchShark
It is Neuschwanstein castle in Bavaria. ...

It is Neuschwanstein castle in Bavaria.

Regards,

Frederic
Forum: Hardware mods 19 October 2011, 20:45
Replies: 736
Views: 159,685
Posted By FrenchShark
I use Icarus verilog along with the musashi 68k...

I use Icarus verilog along with the musashi 68k emulator and a disassembler compiled as a VPI module.
I have a test ROM that is executed by the softcore and by musashi.
After each instruction...
Forum: Hardware mods 16 October 2011, 17:23
Replies: 736
Views: 159,685
Posted By FrenchShark
Hello, I was busy with VHDL/Verilog dev. and...

Hello,

I was busy with VHDL/Verilog dev. and my new job. I did not check my messages for a while.
I like the idea of making FPGA based accelerator, the problem is that the original HW can break...
Forum: Hardware mods 16 October 2011, 14:27
Replies: 736
Views: 159,685
Posted By FrenchShark
I totally agree with Alex, current low cost FPGAs...

I totally agree with Alex, current low cost FPGAs will allow you to get 030 performance. Moreover, Altera Cyclone might not the FPGA with the best performance/price ratio. This might change with the...
Forum: Hardware mods 16 May 2010, 23:58
Replies: 68
Views: 21,919
Posted By FrenchShark
I think I am gonna give a try to a slightly...

I think I am gonna give a try to a slightly different board.
I am putting the 68000 and 6510 footprint on it and directly connect the 40-pin IDC cables on it, with some duct tape :).
BTW, Tobias...
Forum: support.Hardware 16 May 2010, 08:11
Replies: 43
Views: 43,726
Posted By FrenchShark
The Coby TFTV1022 (10 inch wide screen...

The Coby TFTV1022 (10 inch wide screen 800x480)and TFTV1212 (12 inch wide screen 1280x800) does 15KHz through S-Video input and 31KHz+ through VGA input.
Very good choice for an Amiga/Minimig laptop...
Forum: Hardware mods 15 May 2010, 16:38
Replies: 68
Views: 21,919
Posted By FrenchShark
Why not using just two 40-wire IDE cable (we...

Why not using just two 40-wire IDE cable (we cannot use 80-wire cable because of the wrong locations of the GND pins) ?
Then, you stick around the cable some duct tape that you connect to the...
Forum: Hardware mods 08 May 2010, 03:22
Replies: 68
Views: 21,919
Posted By FrenchShark
I have used a similar approach at work with a 50...

I have used a similar approach at work with a 50 pin IDC cable : 25 signals and 25 grounds. The clock speed was around 8 - 10 MHz. I had to put termination resistors of 100 - 120 ohm at the connector...
Forum: Hardware mods 07 May 2010, 02:56
Replies: 68
Views: 21,919
Posted By FrenchShark
Do you know if your quickswitch is compatible...

Do you know if your quickswitch is compatible with the NXP's CBTD3384 ?
It is a 10-bit level shifter with output enable. I have a bunch of them.
Moreover, it does not need the external diode to...
Forum: Hardware mods 25 April 2010, 00:48
Replies: 68
Views: 21,919
Posted By FrenchShark
The Cyclone III has the same issue. The chip is a...

The Cyclone III has the same issue. The chip is a lot better at driving 2.5V and 3.0V I/Os than 3.3V I/Os.
The Cyclone III and IV are indeed very similar. For the moment, just the C4 GX is available...
Forum: request.Other 24 April 2010, 19:11
Replies: 6
Views: 3,924
Posted By FrenchShark
I attended this event too. I lived in Toulouse at...

I attended this event too. I lived in Toulouse at that time.
I remember meeting people from AFLE (IIRC, they are from the Marseille area). Were you with them ?
If you want to meet with Carl, go to...
Forum: Hardware mods 24 April 2010, 14:56
Replies: 68
Views: 21,919
Posted By FrenchShark
Hi, I am interrested too. An FPGA...

Hi,

I am interrested too.
An FPGA accelerator will be fun for my A2000.

Regards,

Frederic
Forum: Hardware pics 11 April 2010, 02:45
Replies: 27
Views: 4,177
Posted By FrenchShark
IIRC, audio line output is 2V peak to peak. So...

IIRC, audio line output is 2V peak to peak. So 6.3V should be enough:p.

Frederic
Forum: Hardware mods 03 April 2010, 03:28
Replies: 362
Views: 72,735
Posted By FrenchShark
I am glad to see that TimeQuest is your friend...

I am glad to see that TimeQuest is your friend now:cool.
From my experience, I have seen SDRAM failing once every 10^9 access.
Exercising the SDRAM for 2 days is a good test.

Regards,

Frederic
Forum: Hardware mods 06 March 2010, 21:34
Replies: 362
Views: 72,735
Posted By FrenchShark
I do not think you can mirror the data since /DSx...

I do not think you can mirror the data since /DSx is not exactly an indication of the requested size.
IIRC, the 680x0 can assert /DS2, /DS1 & /DS0 (then, /DS3 in the following cycle) on an unaligned...
Forum: Hardware mods 06 March 2010, 01:47
Replies: 362
Views: 72,735
Posted By FrenchShark
I had a quick look at the Z3 spec. Do you...

I had a quick look at the Z3 spec.
Do you support Multiple Cycle Transfer ?
If not, can it be the issue with your board especially when the CPU cache does some burst reads or writes?
Can you...
Forum: Hardware mods 01 March 2010, 15:15
Replies: 362
Views: 72,735
Posted By FrenchShark
Is there any jumper on the A4000 to tell :...

Is there any jumper on the A4000 to tell : 0MB/4MB/16MB installed ?

From my own experience, if you have timing issue on the SDRAM, you will see single access working but burst access failing.
Do...
Forum: Hardware mods 28 February 2010, 20:51
Replies: 362
Views: 72,735
Posted By FrenchShark
We will be better off creating a 68000 plug-in...

We will be better off creating a 68000 plug-in board with 64MB of SDRAM and a TG68 in the FPGA : no Zorro II bus space taken, a faster CPU and 64MB of Fast RAM !

Regards,

Frederic
Forum: Hardware mods 14 February 2010, 18:18
Replies: 362
Views: 72,735
Posted By FrenchShark
I am glad the compression trick worked. Are you...

I am glad the compression trick worked. Are you sure that the FPGA correctly configures itself ? I guess you have a config done LED, right ?

Anyway, it is time to use Signaltap ;). Now, you have...
Forum: Hardware mods 13 February 2010, 20:59
Replies: 362
Views: 72,735
Posted By FrenchShark
For SO-8 200mil (there is a 150mil package too) :...

For SO-8 200mil (there is a 150mil package too) :

Macronix 16Mb : MX25L1605D-M2
ST/Numonyx 16Mb : M25P16-VMW
Eon 16Mb : EN25F16-100H
AMIC 16Mb : A25L016M-F
Spansion 16Mb : S25FL016A0LMFI01
...
Forum: Hardware mods 13 February 2010, 16:59
Replies: 362
Views: 72,735
Posted By FrenchShark
Did you compress the SOF ? There is a hidden...

Did you compress the SOF ? There is a hidden option in the "Convert Programming Files" window : select the .sof file under "SOF Data" then hit the button "Properties".

The compatible SPI brands...
Forum: Hardware mods 11 February 2010, 15:16
Replies: 362
Views: 72,735
Posted By FrenchShark
Overshoots and undershoots are overvoltages or...

Overshoots and undershoots are overvoltages or undervoltages you see after a rising or falling edge on the signals. They destroy the I/O cells over time.

They are due to wrong impedance matching...
Forum: Hardware mods 11 February 2010, 14:59
Replies: 362
Views: 72,735
Posted By FrenchShark
All the SPI Flashes I looked at have the same...

All the SPI Flashes I looked at have the same pinout.
Two footprints are available (not counting the QFN) : SOIC-8 and SOIC-16. The SOIC-8 footprint fits inside the SOIC-16 footprint by rotating it...
Forum: Hardware mods 11 February 2010, 03:18
Replies: 362
Views: 72,735
Posted By FrenchShark
Good ! This it what I do also. I...

Good !
This it what I do also.

I personnaly do not use the EPCS chips they are too expensive.
Actually, they are ST/Numonyx chips with a different marking. The Spansion chips work too. Get a...
Showing results 1 to 40 of 155
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