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-   -   Open Source A500 accelerator cooking nicely (http://eab.abime.net/showthread.php?t=85344)

Pat the Cat 31 December 2016 01:11

Open Source A500 accelerator cooking nicely
 
It's called the TerribleFire, and that's how the poster appears on twitter and youtube.

https://www.youtube.com/channel/UCu4...y1ILAxNh7TGsmQ

What makes these (020 and 030) boards a little different is - open source.

You can download the board designs and get them made up by a third party.

Then either add the chips yourself or pay somebody else to do that.

https://github.com/terriblefire/tf520

It's not a Vampire but still pretty good that new boards are being developed. This one on a shoe string budget in Glasgow, Scotland, by Stephen Leary.

:great

idrougge 31 December 2016 02:27

Looks good, but without RAM it's probably a waste of fine 68020 processors.

Pat the Cat 31 December 2016 02:53

1 Attachment(s)
Give him a little credit... look to the right of the CPU.

pandy71 31 December 2016 02:56

http://eab.abime.net/showpost.php?p=...9&postcount=92 - author himself.

Pat the Cat 31 December 2016 02:58

Maybe, but he's never, ever started a thread on this board. According to his profile, anyway.

idrougge 31 December 2016 03:55

Quote:

Originally Posted by Pat the Cat (Post 1131183)
Give him a little credit... look to the right of the CPU.

I looked at the DirtyPCBs link; it must lead to an older revision of the card.

Pat the Cat 31 December 2016 04:01

Well, you are right in saying an accelerator card without memory is a waste of effort... but not true, in this case.

whiteb 31 December 2016 09:34

Quote:

Originally Posted by idrougge (Post 1131195)
I looked at the DirtyPCBs link; it must lead to an older revision of the card.

That is the 020, he is using SRAM on the 030 board he is working on.

The 020 with SRAM is about to be updated to Github, he just wants to make sure its working 100% (Its in the video), he just doesnt want anyone running off to build them before he is happy.

plasmab 31 December 2016 21:45

Hey I just noticed this thread.

Just finished populating the board...

http://uploads.tapatalk-cdn.com/2016...47fcea8b9f.jpg

The FPU and IDE still don't have firmware yet but the SRAM is working (albeit) using the slow async bus at the moment. Will make burst work eventually


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plasmab 31 December 2016 21:52

Quote:

Originally Posted by idrougge (Post 1131178)
Looks good, but without RAM it's probably a waste of fine 68020 processors.

The 020 and (upcoming) 040 boards are meant for research only (let . They wont have RAM (although i might try an SD port on the 040 board and write some drivers for it.

The 030 board is a stab at seeing what can fit on a 10cm x 10cm board.

Pat the Cat 31 December 2016 22:04

Well, I think you're doing great work. Please keep it up. :)

plasmab 01 January 2017 01:24

http://uploads.tapatalk-cdn.com/2016...bfa198ce23.jpg

RAM benchmarks at 16Mhz... not even using STERM yet.

FPU is not working at all... v strange


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Locutus 01 January 2017 01:51

Always great to see these cool hobby projects on the Amiga and complete with code/layout releases is the way to go :-)

Awesome!

whiteb 01 January 2017 03:37

Quote:

Originally Posted by plasmab (Post 1131387)
http://uploads.tapatalk-cdn.com/2016...bfa198ce23.jpg

RAM benchmarks at 16Mhz... not even using STERM yet.

FPU is not working at all... v strange


Sent from my iPhone using Tapatalk

Does the 68030 / 68882 need any special instructions (say in Verilog or CPLD) to make it available at system init ?

plasmab 01 January 2017 03:45

Quote:

Originally Posted by whiteb (Post 1131407)
Does the 68030 / 68882 need any special instructions (say in Verilog or CPLD) to make it available at system init ?

From what I can tell we simply assert the chip select during the correct CPU SPACE cycle. I have used a 32 bit wide bus.. i wonder if that actually causes issues.

whiteb 01 January 2017 04:04

1 Attachment(s)
Quote:

Originally Posted by plasmab (Post 1131409)
From what I can tell we simply assert the chip select during the correct CPU SPACE cycle. I have used a 32 bit wide bus.. i wonder if that actually causes issues.

All I can pick up from the datasheets, is that to configure the 68882 to 32bit bus, A0 and Size must be strapped HIGH. I dont know how that works in the 68030 with FPU on the same chip.

Pat the Cat 01 January 2017 04:08

This any use? Original 1988 datasheet on the 68882.

Probably already got, if you've got that far. :)

http://www.rlocman.ru/i/File/dat/Fre...68882EI16A.pdf

Figure 11, page 14 has some diagrams explaining.

EDIT EDIT: Weird, need +5V on A0 of the 68882... would never have guessed that.

idrougge 01 January 2017 07:32

Quote:

Originally Posted by plasmab (Post 1131344)
The 020 and (upcoming) 040 boards are meant for research only (let . They wont have RAM (although i might try an SD port on the 040 board and write some drivers for it.

The 030 board is a stab at seeing what can fit on a 10cm x 10cm board.

Oh, so it's your card, plasmab. Good to see you're not sticking to the old Frances/Lucas layouts.

plasmab 01 January 2017 11:31

Quote:

Originally Posted by idrougge (Post 1131436)
Oh, so it's your card, plasmab. Good to see you're not sticking to the old Frances/Lucas layouts.

Routing and layout is most of the fun! :)

plasmab 01 January 2017 11:34

Quote:

Originally Posted by Pat the Cat (Post 1131416)
This any use? Original 1988 datasheet on the 68882.

Probably already got, if you've got that far. :)

http://www.rlocman.ru/i/File/dat/Fre...68882EI16A.pdf

Figure 11, page 14 has some diagrams explaining.

EDIT EDIT: Weird, need +5V on A0 of the 68882... would never have guessed that.

Thats what i used for reference and thats how I wired it.

VCC to A0 and SIZ. 32 Bit bus wired and DSACK0/DSACK1 wired to the 030. Not much to go wrong here from what i can tell.

If i get nowhere i'll drop the FPU into memory space and poke at it from there. (One of the amazing things about the CPLD setup i have)


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