Stedy

Stedy... you have email at your iansteadman.co.uk email address.

Hi Rogerio,

I will gladly provide technical assistance where I can. Please bear in mind that I also work on 2 commercial projects in my limited spare time, so my support will be limited. I can review designs and deal with most technical queries.

A few comments on your proposals.

On version 1, why use an FPGA when a CPLD like the Coolrunner may be cheaper. FPGAs need configuration ROMs which cost, sometimes more than the FPGA!

DDR RAM will most likely be slower then SDRAM/SRAM allowing for the overheads and slow speed of the 030. It also requires at least a 4 layer board with 2 power converters to terminate bus cycles.


Maybe one time You, Zetro and I should get together on IRC and brainstorm?

Persevere with Eagle CAD, it is quite a good tool for the money.

Bye,

Ian

Hello Ian.

We want you to check and contribute with the new A600 accelerator board, if you want to.

Hope you join us, m8. We need your guidance and knowledge to accomplish the 2.0 board (1.0 will be simple enough to avoid problems, I hope).

The 1.0 (or mkI, if you like) project is a EC020 or 020/030 plus 4/8Mb sync RAM, using a tiny Xilinx FGPA to manage handshaking and memory address.

2.0 will add SDRAM or EDO up to 256Mb, using a larger FPGA.

3.0 will be the port for A500/2000/equivalents, adding an IDE controller.

DDR RAM was in our thoughts, too. But I didn't find a DDR controller for 68k, only for PPC.

So, as you see, we need guidance, suggestions, and sometimes a shock to keep the design flowing.

And my skills with Eagle and relates sucks. I prefer hand-drawing.

Finishing: we need your help.

Your friend.
Rogério